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features ? built using the advantages and compatibility of cmos and ixys hdmos tm processes ? latch-up protected up to 0.5a ? high peak output current: 4a peak ? wide operating range: 4.5v to 35v ? ability to disable output under faults ? high capacitive load drive capability: 1800pf in <15ns ? matched rise and fall times ? low propagation delay time ? low output impedance ? low supply current ? two identical drivers in single chip applications ? driving mosfets and igbts ? limiting di/dt under short circuit ? motor controls ? line drivers ? pulse generators ? local power on/off switch ? switch mode power supplies (smps) ? dc to dc converters ? pulse transformer driver ? class d switching amplifiers ixdd404 first release copyright ? ixys corporation 2004 general description the ixdd404 is comprised of two 4 amp cmos high speed mosfet drivers. each output can source and sink 4 a of peak current while producing voltage rise and fall times of less than 15ns to drive the latest ixys mosfets & igbt's. the input of the driver is compatible with ttl or cmos and is fully immune to latch up over the entire operating range. designed with small internal delays, cross conduction/current shoot- through is virtually eliminated in the ixdd404. improved speed and drive capabilities are further enhanced by very low, matched rise and fall times. additionally, each driver in the ixdd404 incorporates a unique ability to disable the output under fault conditions. when a logical low is forced into the enable input of a driver, both of it's final output stage mosfets (nmos and pmos) are turned off. as a result, the respective output of the ixdd404 enters a tristate mode and achieves a soft turn-off of the mosfet/ igbt when a short circuit is detected. this helps prevent damage that could occur to the mosfet/igbt if it were to be switched off abruptly due to a dv/dt over-voltage transient. the ixdd404 is available in the standard 8 pin p-dip (pi), soic-8 (sia) and soic-16 (sia-16) packages. for enhanced thermal performance, the sop-8 and sop-16 are also avail- able with an exposed grounded metal back package as the si and si-16 respectively. figure 1 - functional diagram inb ena enb outa outb 200k 200k gnd vcc 4 amp dual low-side ultrafast mosfet driver part number package type temp. range configuration ixdd404pi 8-pin pdip ixdd404si 8-pin soic with grounded metal back IXDD404SIA 8-pin soic ixdd404si-16 16-pin soic with grounded metal back IXDD404SIA-16 16-pin soic -55 c to +125 c dual non inverting with enable ordering information note: mounting or solder tabs on all packages are connected to ground ds99046b(08/04)
2 ixdd404 unless otherwise noted, t a = 25 o c, 4.5v v cc 35v . all voltage measurements with respect to gnd. ixdd404 configured as described in test conditions . all specifications are for one channel. electrical characteristics symbol parameter test conditions min typ max units v ih high input voltage 4.5v v in 18v 2.5 v v il low input voltage 4.5v v in 18v 0.8 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh output resistance @ output high v cc = 18v 2 2.5 ? r ol output resistance @ output low v cc = 18v 1.5 2 ? i peak peak output current v cc = 18v 4 a i dc continuous output current 1 a v en enable voltage range - 0.3 vcc + 0.3 v v enh high en input voltage 2/3 vcc v v enl low en input voltage 1/3 vcc v t r rise time c l =1800pf vcc=18v 16 18 ns t f fall time c l =1800pf vcc=18v 13 17 ns t ondly on-time propagation delay c l =1800pf vcc=18v 36 40 ns t offdly off-time propagation delay c l =1800pf vcc=18v 35 39 ns t enoh enable to output high delay time 30 ns t dold disable to output low disable delay time 30 ns v cc power supply voltage 4.5 18 35 v i cc power supply current v in = 3.5v v in = 0v v in = + v cc 1 0 3 10 10 ma a a r en enable pull-up resistor 200 k ? absolute maximum ratings (note 1) parameter v alue supply voltage 40 v all other pins -0.3 v to v cc + 0.3 v junction temperature 150 o c storage temperature -65 o c to 150 o c lead temperature (10 sec) 300 o c operating ratings parameter v alue operating temperature range -55 o c to 125 o c thermal impedance (junction to ambient) 8 pin pdip (pi) ( ja ) 120 o c/w 8 pin soic (sia) ( ja ) 110 o c/w 8 pin soic (si) ( ja ) with heat sink** heat sink area of 1cm 2 71 o c/w 16 pin soic (sia-16) ( ja ) 110 o c/w note 1: operating the device beyond parameters with listed ?absolute maximum ratings? may cause permanent damage to the device. typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. the guaranteed specifications apply only for the test conditions listed. exposure to absolute maximum rated conditions for extended periods may affect device reliability. specifications to change without notice **heat sink area is 1 oz. copper on one side of .06" thick fr4 soldered to metal back plane.
3 ixdd404 symbol parameter test conditions min typ max units v ih high input voltage 2 v v il low input voltage 2.4 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh output resistance @ output high v cc = 18v 3.4 ? r ol output resistance @ output low v cc = 18v 2 ? i peak peak output current v cc = 18v 3.2 a i dc continuous output current 1 a t r rise time c l =1000pf vcc=18v 11 ns t f fall time c l =1000pf vcc=18v 13 ns t ondly on-time propagation delay c l =1000pf vcc=18v 60 ns t offdly off-time propagation delay c l =1000pf vcc=18v 59 ns v cc power supply voltage 4.5 18 35 v i cc power supply current v in = 3.5v v in = 0v v in = + v cc 1 0 3 10 10 ma a a unless otherwise noted, temperature over -55 o c to 150 o c, 4.5v v cc 35v . all voltage measurements with respect to gnd. ixdd404 configured as described in test conditions . all specifications are for one channel. electrical characteristics specifications to change without notice
4 ixdd404 pin description symbol function description en a a channel enable the channel a enable pin. this pin, when driven low, disables the a channel, forcing a high impedance state to the a channel output. in a a channel input a channel input signal-ttl or cmos compatible. gnd ground the system ground pin. internally connected to all circuitry, this pin provides ground reference for the entire chip. this pin should be connected to a low noise analog ground plane for optimum performance. in b b channel input b channel input signal-ttl or cmos compatible. out b b channel output b channel driver output. for application purposes, this pin is connected, through a resistor, to gate of a mosfet/igbt. vcc supply voltage positive power-supply voltage input. this pin provides power to the entire chip. the range for this voltage is from 4.5v to 35v. out a a channel output a channel driver output. for application purposes, this pin is connected, through a resistor, to gate of a mosfet/igbt. en b b channel enable the channel b enable pin. this pin, when driven low, disables the b channel, forcing a high impedance state to the b channel output. figure 2 - characteristics test diagram caution: these devices are sensitive to electrostatic discharge; follow proper esd procedures when handling and assembling this component. v in en a in a gnd in b en b out a out b vcc 1 2 3 4 8 7 6 5 i x d d 4 0 4 so8 (si) 8 pin dip (pi) so16 (si-16) pin configurations
5 ixdd404 max / min input vs. temperature c l = 1000pf, v cc = 18v 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 -60 -10 40 90 140 190 temperature (c) max / min input voltage min input high max input low rise and fall times vs. temperature c l = 1000pf, v cc = 18v 0 2 4 6 8 10 12 14 -60 -10 40 90 140 190 temperature (c) time (ns) t f t r rise times vs. load capacitance 0 10 20 30 40 50 60 70 80 0 2000 4000 6000 8000 10000 load capacitance (pf) rise time (ns) 8v 10v 12v 18v 25v 35v rise times vs. supply voltage 0 10 20 30 40 50 60 70 80 5 101520253035 supply voltage (v) rise time (ns) 200pf 1000pf 1800pf 4700pf 6800p f 10000pf fall times vs. supply voltage 0 10 20 30 40 50 60 70 80 5 101520253035 supply voltage (v) fall times (ns) 200pf 1000pf 1800pf 4700pf 6800pf 10000pf typical performance characteristics fig. 3 fig. 4 fig. 5 fig. 6 fig. 7 fig. 8 fall times vs. load capacitance 0 10 20 30 40 50 60 70 80 0 2000 4000 6000 8000 10000 load capacitance (pf) fall time (ns) 8v 10v 12v 18v 25v 35v
6 ixdd404 supply current vs. frequency vcc = 8v 0.01 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 200 pf 1000 pf 1800 pf 4700 pf 6800 pf 10000 pf fig. 10 fig. 12 fig. 14 supply current vs. load capacitance vcc = 8v 0 10 20 30 40 50 60 70 80 90 100 100 1000 10000 load capacitance (pf) supply current (ma) 10 khz 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. load capacitance vcc = 12v 0 10 20 30 40 50 60 70 80 90 100 100 1000 10000 load capacitance (pf) supply current (ma) 10 khz 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. load capacitance vcc = 18v 0 10 20 30 40 50 60 70 80 90 100 100 1000 10000 load capacitance (pf) supply current (ma) 10 khz 50 khz 100 khz 500 khz 1 mhz 2 mhz supply current vs. frequency vcc = 12v 0.01 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 200 pf 1000 pf 1800 pf 4700 pf 6800 pf 10000 pf supply current vs. frequency vcc = 18v 0.01 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 200 pf 1000 pf 1800 pf 6800 pf 10000 pf 4700 pf fig. 9 fig. 11 fig. 13
7 ixdd404 quiescent supply current vs. temperature v cc = 18v, v in = 5v@1khz, c l = 1000pf 0 0.05 0.1 0.15 0.2 0.25 0.3 -60 -10 40 90 140 190 temperature (c) quiescent v cc input current(ma) propagation delay vs. input voltage c l = 1800pf v cc = 15v 20 25 30 35 40 45 50 24681012 input voltage (v) propagation delay (ns) t ondly t offdly propagation delay vs. supply voltage c l = 1800pf v in = 5v@1khz 0 10 20 30 40 50 60 70 5 101520253035 supply voltage (v) propagation delay (ns) t ondly t offdly supply current vs. frequency vcc = 35v 0.01 0.1 1 10 100 1000 1 10 100 1000 10000 frequency (khz) supply current (ma) 200 pf 1000 pf 1800 pf 4700 pf 6800 pf 10000 pf supply current vs. load capacitance vcc = 35v 0 10 20 30 40 50 60 70 80 90 100 100 1000 10000 load capacitance (pf) supply current (ma) 10 khz 50 khz 100 khz 1mhz 500 khz 2mhz fig. 16 fig. 15 fig. 17 fig. 18 fig. 19 fig. 20 tondly propagation delay times vs. temperature c l = 1000pf, v cc = 18v 20 25 30 35 40 45 50 55 60 -60 -10 40 90 140 190 temperature (c) time (ns) t ondly t offdly
8 ixdd404 vcc vs. n channel ouput current 0 2 4 6 8 10 12 14 5 101520253035 vcc (v) n channel output current (a) p channel output current vs. temperature v cc = 18v, c l = 1000pf 0 1 2 3 4 5 6 -80 -30 20 70 120 170 temperature (c) p channel output current (a) vcc vs. p channel output current -12 -10 -8 -6 -4 -2 0 5 101520253035 vcc (v) p channel output current (a) low state output resistance vs. supply voltage 0 1 2 3 4 5 6 5 101520253035 supply voltage (v) low state output resistance (ohms) high state ouput resistance vs. supply voltage 0 1 2 3 4 5 6 5 101520253035 supply voltage (v) high state output resistance (ohms) fig. 21 fig. 22 fig. 23 fig. 24 fig. 25 n channel output current vs. temperature v cc = 18v c l = 1000pf 0 1 2 3 4 5 6 -80 -30 20 70 120 170 temperature (c) n channel output current (a) fig. 26
9 ixdd404 figure 28 - typical application short circuit di/dt limit enable threshold vs. supply voltage 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 supply voltage (v) enable threshold (v) fig. 27
10 ixdd404 applications information short circuit di/dt limit a short circuit in a high-power mosfet such as the ixfn100n20, (20a, 1000v), as shown in figure 26, can cause the current through the module to flow in excess of 60a for 10 s or more prior to self-destruction due to thermal runaway. for this reason, some protection circuitry is needed to turn off the mosfet module. however, if the module is switched off too fast, there is a danger of voltage transients occuring on the drain due to ldi/dt, (where l represents total inductance in series with drain). if these voltage transients exceed the mosfet's voltage rating, this can cause an avalanche break- down. the ixdd404 has the unique capability to softly switch off the high-power mosfet module, significantly reducing these ldi/dt transients. thus, the ixdd404 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients. the ixdd404 is designed to not only provide 4a per output under normal conditions, but also to allow it's outputs to go into a high impedance state. this permits the ixdd404 output to control a separate weak pull-down circuit during detected overcurrent shutdown conditions to limit and separately con- trol d vgs /dt gate turnoff. this circuit is shown in figure 27. referring to figure 27, the protection circuitry should include a comparator, whose positive input is connected to the source of the ixfd100n20. a low pass filter should be added to the input of the comparator to eliminate any glitches in voltage caused by the inductance of the wire connecting the source resistor to ground. (those glitches might cause false triggering of the comparator). the comparator's output should be connected to a srff( set reset flip flop). the flip-flop controls both the enable signal, and the low power mosfet gate. please note that cmos 4000- series devices operate with a v cc range from 3 to 15 vdc, (with 18 vdc being the maximum allowable limit). a low power mosfet, such as the 2n7000, in series with a resistor, will enable the ixfn100n20 gate voltage to drop gradually. the resistor should be chosen so that the rc time constant will be 100us, where "c" is the miller capacitance of the ixfn100n20. for resuming normal operation, a reset signal is needed at the srff's input to enable the ixdd404 again. this reset can be generated by connecting a one shot circuit between the ixdd408 input signal and the srff restart input. the one shot will create a pulse on the rise of the ixdd404 input, and this pulse will reset the srff outputs to normal operation. when a short circuit occurs, the voltage drop across the low- value, current-sensing resistor, (rs=0.005 ohm), connected between the mosfet source and ground, increases. this triggers the comparator at a preset level. the srff drives a low input into the enable pin disabling the ixdd404 output. the srff also turns on the low power mosfet, (2n7000). in this way, the high-power mosfet module is softly turned off by the ixdd404, preventing its destruction. 10uh ld 0.1ohm rd rs 20nh ls 1ohm rg 10kohm r+ ixfn100n20 high_power 5kohm rcomp 100pf c+ + - v+ v- comp lm339 1600ohm rsh ccomp 1pf vcc vcca in en dgnd sub out ixdd404 + - vin + - vcc + - ref + - vb cd4001a nor2 1mohm ros not2 cd4049a cd4011a nand cd4049a not1 cd4001a nor1 cd4049a not3 low_power 2n7002/plp 1pf cos 0 s r en q one shot circuit sr flip-flop figure 29 - application test diagram
11 ixdd404 10k r3 3.3k r2 q1 2n3904 en output cc (from gate driver po w e r s upply) input) t t l cmos 3.3k r1 v dd (from logic po w e r s upply) or high voltage (t o ixdd404 en i n p u t ) supply bypassing and grounding practices, output lead inductance when designing a circuit to drive a high speed mosfet utilizing the ixdd404, it is very important to keep certain design criteria in mind, in order to optimize performance of the driver. particular attention needs to be paid to supply bypassing , grounding , and minimizing the output lead inductance . say, for example, we are using the ixdd404 to charge a 2500pf capacitive load from 0 to 25 volts in 25ns . using the formula: i= ? v c / ? t, where ? v=25v c=2500pf & ? t=25ns we can determine that to charge 2500pf to 25 volts in 25ns will take a constant current of 2.5a. (in reality, the charging current won?t be constant, and will peak somewhere around 4a). supply bypassing in order for our design to turn the load on properly, the ixdd404 must be able to draw this 2.5a of current from the power supply in the 25ns. this means that there must be very low impedance between the driver and the power supply. the most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (these capacitors should be carefully selected, low inductance, low resistance, high-pulse current-service capacitors). lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the ixdd404 to an absolute minimum. grounding in order for the design to turn the load off properly, the ixdd404 must be able to drain this 2.5a of current into an adequate grounding system. there are three paths for returning current that need to be considered: path #1 is between the ixdd404 and it?s load. path #2 is between the ixdd404 and it?s power supply. path #3 is between the ixdd404 and whatever logic is driving it. all three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. in addition, every effort should be made to keep these three ground paths distinctly separate. otherwise, (for instance), the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the ixdd404. output lead inductance of equal importance to supply bypassing and grounding are issues related to the output lead inductance. every effort should be made to keep the leads between the driver and it?s load as short and wide as possible. if the driver must be placed farther than 2? from the load, then the output leads should be treated as transmission lines. in this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connect directly to the ground terminal of the load. ttl to high voltage cmos level translation the enable (en) input to the ixdd404 is a high voltage cmos logic level input where the en input threshold is ? v cc , and may not be compatible with 5v cmos or ttl input levels. the ixdd404 en input was intentionally designed for enhanced noise immunity with the high voltage cmos logic levels. in a typical gate driver application, v cc =15v and the en input threshold at 7.5v, a 5v cmos logical high input applied to this typical ixdd404 application?s en input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. the note below is for optional adaptation of ttl or 5v cmos levels. the circuit in figure 28 alleviates this potential logic level misinterpretation by translating a ttl or 5v cmos logic input to high voltage cmos logic levels needed by the ixdd404 en input. from the figure, v cc is the gate driver power supply, typically set between 8v to 20v, and v dd is the logic power supply, typically between 3.3v to 5.5v. resistors r1 and r2 form a voltage divider network so that the q1 base is positioned at the midpoint of the expected ttl logic transition levels. a ttl or 5v cmos logic low, v ttllow =~<0.8v, input applied to the q1 emitter will drive it on. this causes the level translator output, the q1 collector output to settle to v cesatq1 + v ttllow =<~2v, which is sufficiently low to be correctly interpreted as a high voltage cmos logic low (<1/3v cc =5v for v cc =15v given in the ixdd404 data sheet.) a ttl high, v ttlhigh =>~2.4v, or a 5v cmos high, v 5vcmoshigh =~>3.5v, applied to the en input of the circuit in figure 28 will cause q1 to be biased off. this results in q1 collector being pulled up by r3 to v cc =15v, and provides a high voltage cmos logic high output. the high voltage cmos logical en output applied to the ixdd404 en input will enable it, allowing the gate driver to fully function as a 4 amp output driver. the total component cost of the circuit in figure 28 is less than $0.10 if purchased in quantities >1k pieces. it is recommended that the physical placement of the level translator circuit be placed close to the source of the ttl or cmos logic circuits to maximize noise rejection. figure 30 - ttl to high voltage cmos level translator
12 ixdd404 ixys semiconductor gmbh edisonstrasse15 ; d-68623; lampertheim tel: +49-6206-503-0; fax: +49-6206-503627 e-mail: marcom@ixys.de ixys corporation 3540 bassett st; santa clara, ca 95054 tel: 408-982-0700; fax: 408-496-0670 e-mail: sales@ixys.net dimenional outline: ixdd404pi dimenional outlines: ixdd404si-ct and IXDD404SIA dimenional outlines: ixdd404si-16ct and IXDD404SIA-16

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